LDMOSFETs (Laterally Diffused MOSFETs) are known. Such devices are used as high-voltage switches and components in devices fabricated in various MOS process (fabrication) technologies including logic CMOS and the like, but having a need for relatively high-voltage capabilities (e.g., 10 volts in a 3.3 volt process). Such high-voltages are used in charge pumps, programming nonvolatile memory circuits, on-chip liquid crystal display drivers, on-chip field-emission display drivers, and the like. A typical LDMOSFET 10 (also referred to as an LDMOS) is shown in elevational cross-section in FIG. 1. LDMOS 10 is formed in a substrate 12 of p-type conductivity. A first heavily doped region of n-type conductivity (“first n+ region”) 13 is disposed in a first well of a p-type conductivity (“first p− well”) 14 of the substrate 12. A source terminal 16 is coupled to the first n+ region 13. A heavily doped region of p-type conductivity (“p+ region”) 18 is disposed in a second well of p-type conductivity (“second p− well”) 15. A p+ doped region 18 is disposed in second p− well 15. A body terminal 20 is coupled to p+ doped region 18. A well of n-type conductivity (“n− well”) 22 is disposed in the substrate 12 between the first p− well 14 and the second p− well 15. A first isolation structure 23, such as a first trench 24, is disposed in the n− well 22. The first isolation structure 23 such as first trench 24 is filled with an insulating dielectric material such as silicon dioxide which may be deposited or grown in any convenient manner such as using the well-known Shallow Trench Isolation (STI) process (as shown) or the well-known Local Oxidation of Silicon (LOCOS) process (not shown). A second heavily doped region of the n-type conductivity (“second n+ region”) 28 is disposed in the n− well 22. A drain terminal 30 is coupled to the second n+ region 28. A second isolation structure 25, such as a trench 26, is disposed at least partially in the n− well 22, and acts to isolate second the n+ region 28 from the p+ region 18. A layer of dielectric 33 is disposed over a portion of the first p− well 14, the p− well/n− well junction region 34, a portion of n− well 22 and a portion of the first trench 24. In fact, the material of dielectric 33 may be the same as the material of first trench 24, if desired. A gate 32 is in contact with the dielectric layer 33 as well as the dielectric material in the first trench 24. Gate region 32 may comprise n+ doped polysilicon material, p+ doped polysilicon material, metal, or any other suitable material used for forming a conductive gate. Insulating sidewall spacers 36 and 38 are also provided. The channel of the device extends from the source region 13 to the first isolation structure 23, as shown. The region denoted Lw is a region of lateral diffusion of the n− well 22 under the gate and Lw denotes its length.
In this device the n− well 22 is used as the drain of the device. A high breakdown voltage is provided due to lateral diffusion in the region denoted Lw under the gate. This structure results in deep junctions with lower doping than that of a typical n+ drain. The breakdown voltage is determined by the doping concentrations in the n− well 22 (approximately 1017 atoms/cm3) and p− well 14 (approximately 1017 atoms/cm3) of the n-well/p-well junction 34. The prior art embodiment shown uses shallow trench isolation (STI). Similar embodiments implementing a LOCOS isolation scheme are also well known in the art.
P-Channel high-voltage MOSFETs are also known. Turning now to FIG. 2, such a device 40 is illustrated in elevational cross section. The device 40 is fabricated in an n− well 42 of a substrate of p-type conductivity (“p-substrate”) 44. Its source 46 is a heavily doped diffusion region of p-type conductivity, disposed in n− well 42. Its drain 48 is a heavily doped diffusion region of p-type conductivity, formed in a lightly doped diffusion region 50 of p-type conductivity, which can be formed out of a “channel stop” implant using boron doping. A body contact 52 is formed by an n+ diffusion in the n− well 42. A gate 54 formed of a conductive material such as heavily doped polysilicon or metal overlies a layer of dielectric 55 (such as Silicon dioxide gate oxide) which, in turn, overlies a portion of the source region 46 and the p-diffusion region 50 as shown. A pair of isolation structures 56 and 58 such as field oxide formed with a LOCOS (local oxidation of silicon) process or an STI (shallow trench isolation) process are formed on either side of the drain region 48. The p− diffusion region 50 extends from insulating structure 58, under drain region 48 and under insulating structure 56. The breakdown voltage is determined by the doping concentrations in the n− well 42 (approximately 1017 atoms/cm3) and p− diffusion region 50 (approximately 1017 atoms/cm3) of the n-well/p-diffusion junction 59.
As device geometries and minimum feature sizes (MFS) shrink, e.g., from 0.18 micron MFS to 0.13 micron MFS to 0.09 micron MFS and beyond, new ways to provide relatively high breakdown voltages, particularly in standard CMOS processes, become more and more important. Accordingly, it is highly desirable to provide an improved high-voltage switching device. It is also highly desirable to provide an n-channel and a p-channel high-voltage switching device, so that a high-voltage CMOS inverter and high-output-voltage analog amplifier as well as a circuit with a relatively high voltage output for a relatively low input voltage Vdd may be fabricated.